Multicore mixed-signal ASIC for sensors and encoders interfacing


As the need for sensors and encoders grows exponentially, all the value chain must also evolve in order to maintain coherence and economic sense. For a customer active in the industry market, IC’Alps provided a multicore ASIC able to interface with a great variety of sensors and encoders.

Customer request

To design and implement the digital partition of a multicore mixed-signal ASIC with multiple sensor interfaces.

Work in progress

Our approach

The project started with a specification phase to define the required configuration for CPU and standard peripherals, memory strategy, custom peripheral characteristics and industrial test strategy (scan, Memory Built-In Self Test [MBIST], eFlash…).

MCU sub-system was then built step by step targeting both ASIC technology – with preliminary synthesis and place-and-route runs to check PPA performance – and FPGA technology for Customer validation on a dedicated breadboard embedding targeted sensors to check system performance.

UVM testbench was built by IC’Alps to check MCU assembly and main functions.

ASIC features


RISC-V dual-core architecture

Die size <15mm2


Partition Features

~350 Kgates - 23KB Memory bits - 128KB Flash bits

Frequency > 64 MHz

Size <8mm2

Want to design your own ASIC ?

Let's get in touch with our Business Managers for an initial discussion or to request an ASIC Design Consultation