At Neurallys, we are developping an implantable medical device for remote monitoring of the intracranial pressure, for patients suffering from hydrocephalus. We selected IC’Alps to analyze our electronics under the prism of ASIC through a feasibility study. Their analysis provided our R&D team with very valuable information about achievable performances, size and development costs for an ASIC based integration, including various scenarii. This study demonstrated clear advantages of the ASIC approach to improve the size and the power consumption of our system, especially when miniaturization becomes an enabler to penetrate our market

IC’Alps’ approach to collaborative working has given ENSTA Bretagne flexibility and the security of opened discussions. A synergy of expertise has been an important factor to beat the challenge of quick realization of a functional first silicon demonstrator of our eFPGA technology. We are happy to announce that the first demonstrator in TSMC 55 nm ULP process technology is back from fab and tested fully functional

X-FAB as a specialty foundry relies on skilled and experienced partners. We are very happy to have IC’Alps joining our partner program, so that our customers can leverage from their expertise in mixed-signal IC design and supply chain management

We needed some custom designed IP blocks to open up the door to differentiation for a new chip design targeting imaging applications. In a context of increased competition, delayed delivery of this new chip would have certainly shorten our revenue. That’s why it was crucial for us to manage cost and delay but not at the expense of quality. IC’Alps design team delivered custom IP blocks to the agreed specification, on-time and to budget! We definitely recommend their expertise to any fabless company looking for an IP customization that differentiates your product, ensures IP quality, and delivers first-time right silicon

We were extremely pleased with IC’Alps’ work on our demo chip for SkyWater’s 130nm process. The IC’Alps team is highly skilled with all aspects of physical implementation, from RTL-to-GDS implementation to tape-out. They met schedule and quality targets, and the chip is fully functional.