IP components internal asset

Set of primary blocks we use when designing your ASIC/SoC

IC’Alps enriched this library of in-house IPs over the years by design experience and technical achievements.

By using them as they are or modify them to fit customer’s needs, our team improves performance & design time and helps offer differentiated IC architectures. It reduces development risks and costs while contributing to first-time-right project execution.

Overall, this approach allows IC’Alps to better serve our customers when designing their ASIC/SoC.

IP strategy

We develop our own IP component library to assess the reachable performance and gather experience for future ASIC integration.

Our IP solutions have been silicon verified in one or more technological nodes and are scalable and portable with respect to foundry’s specific manufacturing process.

We also delivers IP customization services to provide our customers with the IP solution that perfectly match their system requirements

In-house IP components

The following in-house IP components are available to our customers to complement our third-party IP partnerships.

Our design team has been developing world-class IP solutions for use in custom analog or mixed-signal ASICs
  • Oscillators
  • Clock generators
  • Linear regulators
  • Sigma Delta ADCs
  • SAR ADCs
  • On-chip temperature monitors
  • Analog Front-End (AFEs)
  • Charge pumps
  • Voltage references
  • And many others

Single-Channel, 12-Bit, 1-MSPS SAR ADC IP

12-bit general purpose Analog-to-Digital Converter (ADC) with a sampling rate up to 1-MSPS.

Web - HighRes

High-Resolution bipolar ECG/EGM acquisition chain

Ultra-low power analog front-end (AFE) readout circuit designed for wearable and implantable medical devices. Clinical-grade electrocardiogram (ECG) waveforms and QRS detection

Web - Nanopower

Nanopower unipolar ECG/EGM acquisition chain

Nanopower unipolar acqusition chain for intracardiac pacemaker

Accelerate your ASIC design

Time Savings

Through capitalization of our IP library and re-use of standard blocks

Lower Costs

Compared to full in-house design

Reduced Risks

With silicon proven subsystems

Best Performance

Across a variety of technologies