IC’Alps enriched this library of in-house IPs over the years by design experience and technical achievements.
By using them as they are or modify them to fit customer’s needs, our team improves performance & design time and helps offer differentiated IC architectures. It reduces development risks and costs while contributing to first-time-right project execution.
Overall, this approach allows IC’Alps to better serve our customers when designing their ASIC/SoC.
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IP strategy
We develop our own IP component library to assess the reachable performance and gather experience for future ASIC integration.
Our IP solutions have been silicon verified in one or more technological nodes and are scalable and portable with respect to foundry’s specific manufacturing process.
We also delivers IP customization services to provide our customers with the IP solution that perfectly match their system requirements
In-house IP components
The following in-house IP components are available to our customers to complement our third-party IP partnerships
Our design team has been developing world-class IP solutions for use in custom analog or mixed-signal ASICs
- Oscillators
- Clock generators
- Linear regulators
- Sigma Delta ADCs
- SAR ADCs
- On-chip temperature monitors
- Analog Front-End (AFEs)
- Charge pumps
- Voltage references
- And many others
Examples
Single-Channel, 12-Bit, 1-MSPS SAR ADC IP
12-bit general purpose Analog-to-Digital Converter (ADC) with a sampling rate up to 1-MSPS.
High-Resolution bipolar ECG/EGM acquisition chain
Ultra-low power analog front-end (AFE) readout circuit designed for wearable and implantable medical devices. Clinical-grade electrocardiogram (ECG) waveforms and QRS detection
Nanopower unipolar ECG/EGM acquisition chain
Nanopower unipolar acqusition chain for intracardiac pacemaker
We provide the soft IP and required expertise to uniquely combine hardware security features and low-power in a custom ASIC solution for the needs of IoT and medical applications, or more generally serving the need of unique identifier (such as a fingerprint) in either FPGA or ASIC technologies.
Our TRNG and PUF are based on asynchronous solutions, using only standard cells (no specific cells or memories), and providing performances (bit rate generation) > 100x than classical SRAM-based solutions
- STRNG (True Random Number Generator based on a Self-Timed Ring Oscillator)
- STRPUF (Physically Unclonable Function based on a Self-Timed Ring Oscillator)
- QSPI
- SPI controller
- I2C controller
- UART controller
Accelerate your ASIC design
Time Savings
Through capitalization of our IP library and re-use of standard blocks
Lower Costs
Compared to full in-house design
Reduced Risks
With silicon proven subsystems
Best Performance
Across a variety of technologies
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