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FPGA to ASIC Migration

Application

This feasibility study was requested for a niche market.

An ASIC is typically well-suited for this kind of market where a logic design initially prototyped on an FPGA may need more protection, when a FPGA approaches its end-of-life or when the Customer identified the final specifications after testing his application on a FPGA.

Customer request

The customer asked for a feasibility study for a FPGA to ASIC migration.

This study aimed at assessing the reachable performances in an ultra advanced node technology, challenging frequency requirement and a high-level of integration.

The objective is to upgrade the performance of the current customer’s FPGA-based platform.

Our approach

For this, the Customer provided IC’Alps with an RTL code of timing critical blocks and IC’Alps performed topographical synthesis in order to assess the maximum reachable frequency (above the gigahertz), the power consumption and area. Working in close collaboration with the Customer to substitute FPGA-oriented macros with standard cell synthesizable equivalent functions,  IC’Alps created the memory timing models required for a typical ASIC flow and performed several synthesis:

  • with low VT standard cell libraries
  • at different voltages
  • with different RTL datapath configurations
  • with different floorplan configurations (automatic floorplan generation or guided floorplan). IC’Alps made some recommendations and some proposals for the ASIC development

With this feasibility study, the Customer had the confirmation that the targeted performances could be reached and went on the next phase of the project: ASIC specification and technico-economic analysis in order to provide all necessary information for a well-informed decision.

ASIC features

< 22nm technology
ISO9001

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