Tiempo Secure is relying on IC’Alps’ expertise in physical design implementation to develop the hard macro of its Secure Element named TESIC, from netlist to GDSII.
Tiempo Secure’s TESIC includes a secure MCU, secure cryptographic processors and hardware accelerators, security sensors, secure memories and standard interfaces for easy integration and test.
While TESIC is already available on multiple silicon processes, including GF 55 and TSMC 40, the hard macro is now implemented by IC’Alps in GF 22 and TSMC 16.
By collaborating with IC’Alps for back-end implementation, Tiempo is now able to provide its customers with a wider choice in terms of technology
Download the Press Release
English version French version
