HomeExpertiseLow power ASIC

With the ever-increasing market demand for low-energy devices and extended battery life, power budget is a key concern of our customers.

Thus, all contributors committed to the project success – including the provider of integrated circuits (ASIC) – need to be “power saving” aware.

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Power management techniques

Selecting the appropriate process node and the best silicon IP is critical to the success of any low power ASIC project. Most of semiconductor technology providers enable the use of vth variant or biasing scheme. At this step, our analog and logic designers are able to draw benefits from their experiments in order to lead our customers in making the best choice.

For several years a wide spread of design approaches have been developed to address this demand for high power performance. Mastering all of them is mandatory to ensure successful implementation of a wide variety of low power circuit architectures. For example, an always-on circuit may require switching and dynamic power optimization through use of adaptive voltage scaling or dynamic frequency adjustment. Another circuit architecture, most of the time awaiting for event, will require achieving the lowest leakage power. Such concerns at circuit architecture level are the cornerstone of power optimization. Indeed determining where and when the right strategy must be used is the key to success.

At IC’Alps, we have developed strong experience, along with maturity proven design flow and early power estimation solutions (enabling aggressive approaches) leading to the energy efficiency required for your application.

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