Low-power & fast RISC-V-based SoC for Virtual Reality Device

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Application

Embedding more and more intelligence directly into a Virtual Reality Device (VRD) is the major step that manufacturers are currently taking. Designing an ASIC is one of the safest way to go considering the challenging specifications of such integration: consumption, speed and miniaturization.

Customer request

IC’Alps was responsible for the overall integration of all parts. Particularly, IC’Alps was tasked with the design and test services of a physical implementation of a RISC-V based chip in the advanced and challenging TSMC 16nm FinFET technology node, embedding a new class of resistive RAM.

 

Challenges

  • High application requirements: high speed combined with low power
  • MPW shuttle: tight deadline
  • 4-partner project: n4 logistical, legal, management and scope of work challenges to address

 

Specific requirements

  • From both Customer and Founder, work was to be done in a secure environment matching stringent requirements : isolated network, encrypted exchanges, dedicated server, CCTV …
  • 9 RISC-V cores
  • Die size: >15mm2
  • Chip size: >6x6mm2
  • Memory: 50%
  • 15M eq Nand2 gates
  • 4M instances

Our approach

IC’Alps first performed a technology assessment with a first synthesis on a RTL code PULP platform. The aim was to make sure that the flow was properly set and get a first performance assessment in the targeted technology.

As a hierarchical integration was not possible due to planning constraints, IC’Alps then performed a flattened physical implementation of the chip starting from the RTL netlist delivered by the Front-End (FE) partner, using third-party IPs (Standard cells, IO, memories) and project partner RAM. A flattened floorplan meant project time optimization but at the cost of fewer outputs for which the team had to adjust.

After these first challenges were addressed, the team then moved on to synthesis, P&R, complete Sign-off verifications completing GDSII delivery and MPW scheduled shuttle

Finally, post-layout simulations were performed using FE partner test bench and test vectors for global power assessment before final delivery to the customer.

Project Features

RISC-V-based CPU
TSMC 16FFC chip
Fast and Low power ASIC

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