Asynchronous Secured IP block implementation
Design services to perform the physical implementation of an asynchronous secured IP in TSMC 16nm FFC technology (then GF22), starting from a post-synthesis netlist, using third-party IPs, with shield and AO (Always On) Power domain.
This project used asynchronous standard cells from the library previously developed.
- EN9100 quality management system
- Task to be done by IC’Alps in a common criteria environment (isolated network, CCTV, encryption, etc.)
In accordance to customer requirements, the first task was to prepare and implement all criterias compliant with Common Criteria. This implementation was audited by CESTI with a final approval from ANSSI.
This asynchronous design was based on the advanced and challenging TSMC 16FFC (FinFET Compact) technology node using digital Low Power flow.
For this project, our digital team performed :
- the handoff of the post-synthesis Database delivered by customer along with the data acceptance of the third party IP database (standard cells, memories, sensors…)
- the floorplan with early macro area assessment
- Place&Route iterations
- Complete SignOff verifications including Self-heating analysis (a specific requirement when using 16FFC), including static timing analysis for asynchronous design.
Our customer’s tesimonial: « For this project, IC’Alps have been the perfect partner: accurate technical discussions, very efficient and great flexibility ». Learn more here.
From this first successful project came iterations on other technologies.
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