{"id":8233,"date":"2020-09-04T11:58:41","date_gmt":"2020-09-04T09:58:41","guid":{"rendered":"https:\/\/www.icalps.com\/?p=8233"},"modified":"2024-02-07T18:09:58","modified_gmt":"2024-02-07T17:09:58","slug":"ensta-selects-icalps-for-efpga-implementation","status":"publish","type":"post","link":"https:\/\/www.icalps.com\/fr\/ensta-selects-icalps-for-efpga-implementation\/","title":{"rendered":"ENSTA selects IC\u2019Alps for eFPGA implementation"},"content":{"rendered":"<h2 style=\"text-align: center;\">About eFPGA<\/h2>\n<p>&nbsp;<\/p>\n<p>An embedded FPGA (eFPGA) is a programmable IP core integrated into SoCs or custom ICs (ASIC).<\/p>\n<p>eFPGA technology is winning converts among system architects because market requirements are constantly changing and integrated circuits are becoming increasingly complex and expensive to develop<\/p>\n\t\t<div data-elementor-type=\"container\" data-elementor-id=\"50363\" class=\"elementor elementor-50363\" data-elementor-post-type=\"elementor_library\">\n\t\t\t\t<div class=\"elementor-element elementor-element-eb24cb1 e-flex e-con-boxed e-con e-parent\" data-id=\"eb24cb1\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;jet_parallax_layout_list&quot;:[]}\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t<div class=\"elementor-element elementor-element-416bad9 e-con-full e-flex e-con e-child\" data-id=\"416bad9\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;jet_parallax_layout_list&quot;:[]}\">\n\t\t\t\t<div class=\"elementor-element elementor-element-21cd492 elementor-widget elementor-widget-jet-listing-dynamic-image\" data-id=\"21cd492\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"jet-listing-dynamic-image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<div class=\"jet-listing jet-listing-dynamic-image\" ><\/div>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-4a85362 e-con-full e-flex e-con e-child\" data-id=\"4a85362\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;jet_parallax_layout_list&quot;:[]}\">\n\t\t<div class=\"elementor-element elementor-element-db9a051 e-con-full e-flex e-con e-child\" data-id=\"db9a051\" data-element_type=\"container\" data-e-type=\"container\" data-settings=\"{&quot;jet_parallax_layout_list&quot;:[]}\">\n\t\t\t\t<div class=\"elementor-element elementor-element-841804d elementor-blockquote--skin-quotation elementor-widget elementor-widget-blockquote\" data-id=\"841804d\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"blockquote.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<blockquote class=\"elementor-blockquote\">\n\t\t\t<p class=\"elementor-blockquote__content\">\n\t\t\t\t<p>Adding eFPGA functionality to ASIC designs brings the flexibility and performance of programmable logic without the cost, but with better power, performance, throughput and latency.<\/p>\n\t\t\t<\/p>\n\t\t\t\t\t\t\t<div class=\"e-q-footer\">\n\t\t\t\t\t\t\t\t\t\t\t<cite class=\"elementor-blockquote__author\"><p><strong>Th\u00e9otime Bollengier<\/strong>,<span class=\"testimonial-author-desc\">IC architect at ENSTA Bretagne<\/span><\/p>\n<\/cite>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/blockquote>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\n<p>&nbsp;<\/p>\n<h3 class=\"heading_title\" style=\"text-align: center;\">A first demonstrator in TSMC 55 nm ULP process technology back from fab and tested fully functional<\/h3>\n<p>&nbsp;<\/p>\n<ul>\n<li>3200 4-inputs look-up tables (LUTs)<\/li>\n<li>Standard cell based to enable seamless generation from an RTL netlist<\/li>\n<li>Technology independent core (standard cell based)<\/li>\n<li>Fully integrated into standard RTL design flows<\/li>\n<li>Generated and programmed with ENSTA\u2019s ArGen framework<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<p>IC\u2019Alps was handed the responsibility of silicon implementation and prototyping, both needed to make a first demonstrator of ENSTA\u2019s technology. The company was in charge of IC definition, foundry process selection, design (synthesis, floorplan, IO ring, place &amp; route), design for testability, post layout simulations and verifications before launch in fabrication. IC\u2019Alps took in charge the required supply chain management including selection of partners, fabrication, and package assembly.<\/p>\n<p>&nbsp;<\/p>\n<p><img fetchpriority=\"high\" decoding=\"async\" class=\"size-full wp-image-22481 alignleft\" src=\"https:\/\/www.icalps.com\/wp-content\/uploads\/2021\/07\/logo-icalps-partnership-anysilicon.png\" alt=\"IC'Alps Logo\" width=\"250\" height=\"250\" srcset=\"https:\/\/www.icalps.com\/wp-content\/uploads\/2021\/07\/logo-icalps-partnership-anysilicon.png 250w, https:\/\/www.icalps.com\/wp-content\/uploads\/2021\/07\/logo-icalps-partnership-anysilicon-150x150.png 150w\" sizes=\"(max-width: 250px) 100vw, 250px\" \/><\/p>\n<blockquote><p>&nbsp;<\/p>\n<p>Our Team has supported ENSTA-Bretagne from ASIC specification, reached tape-out and delivered packaged dies on-time, even during this COVID period. Last but not least, the team demonstrated its implication to reach first silicon good silicon.<\/p>\n<p><strong>Jean-Luc Triouleyre<\/strong>,<span class=\"testimonial-author-desc\">CEO of IC\u2019Alps<\/span><\/p><\/blockquote>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: center;\"><a class=\"wpb_button_a wpb_button wpb_btn_yellow wpb_btn-large wpb_sharp \" title=\"Download the announcement \" href=\"https:\/\/www.icalps.com\/wp-content\/uploads\/2020\/09\/Press-Release-ENSTA-ICAlps-2.pdf\" target=\" _blank\" rel=\"noopener\"><span class=\"icon-left\">Download the announcement [EN]<\/span><\/a><\/p>\n<p style=\"text-align: center;\"><a class=\"wpb_button_a wpb_button wpb_btn_yellow wpb_btn-large wpb_sharp \" title=\"T\u00e9l\u00e9chargement\" href=\"https:\/\/www.icalps.com\/wp-content\/uploads\/2020\/09\/Annonce-de-presse-ENSTA-ICAlps-1.pdf\" target=\" _blank\" rel=\"noopener\"><span class=\"icon-left\">T\u00e9l\u00e9charger le communiqu\u00e9 [FR]<\/span><\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>The first demonstrator in TSMC 55 nm ULP process technology is back from fab and tested fully functional&#8230;<\/p>\n","protected":false},"author":8,"featured_media":8240,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_seopress_robots_primary_cat":"none","_seopress_titles_title":"","_seopress_titles_desc":"IC\u2019Alps and ENSTA Bretagne announced successful implementation of an embedded FPGA (eFPGA) core on silicon.","_seopress_robots_index":"","footnotes":""},"categories":[108,136],"tags":[],"applications":[],"expertises":[],"services":[],"class_list":{"0":"post-8233","1":"post","2":"type-post","3":"status-publish","4":"format-standard","5":"has-post-thumbnail","7":"category-in-the-press","8":"category-icalps-news"},"_links":{"self":[{"href":"https:\/\/www.icalps.com\/fr\/wp-json\/wp\/v2\/posts\/8233","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.icalps.com\/fr\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.icalps.com\/fr\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.icalps.com\/fr\/wp-json\/wp\/v2\/users\/8"}],"replies":[{"embeddable":true,"href":"https:\/\/www.icalps.com\/fr\/wp-json\/wp\/v2\/comments?post=8233"}],"version-history":[{"count":0,"href":"https:\/\/www.icalps.com\/fr\/wp-json\/wp\/v2\/posts\/8233\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.icalps.com\/fr\/wp-json\/wp\/v2\/media\/8240"}],"wp:attachment":[{"href":"https:\/\/www.icalps.com\/fr\/wp-json\/wp\/v2\/media?parent=8233"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.icalps.com\/fr\/wp-json\/wp\/v2\/categories?post=8233"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.icalps.com\/fr\/wp-json\/wp\/v2\/tags?post=8233"},{"taxonomy":"applications","embeddable":true,"href":"https:\/\/www.icalps.com\/fr\/wp-json\/wp\/v2\/applications?post=8233"},{"taxonomy":"expertises","embeddable":true,"href":"https:\/\/www.icalps.com\/fr\/wp-json\/wp\/v2\/expertises?post=8233"},{"taxonomy":"services","embeddable":true,"href":"https:\/\/www.icalps.com\/fr\/wp-json\/wp\/v2\/services?post=8233"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}